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| mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 1 - advance information document title multi-chip package memory 64m bit (4mx16) dual bank nor flash memory / 8m(512kx16) full cmos sram the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision history revision no. 0.0 remark advance history advance information draft date sep. 7, 2001
mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 2 - advance information multi-chip package memory 64m bit (4mx16) dual bank nor flash memory / 8m(512kx16) full cmos sram the k5c6481n(b)m featuring single 3.0v power supply is a multi chip package memory which combines 64mbit dual bank flash and 8mbit fcmos sram. the 64mbit flash memory is organized as 4m x16 bit and 8mbit sram is organized as 1m x16 bit. the 64mbit flash memory is the high performance non-volatile memory fabricated by cmos technology for peripheral circuit and dinor iv(diveded bit-line nor iv) architecture for the memory cell. all memory blocks are locked and can be programmed or erased, when f-wp is low. using software lock release function, program erase operation can be executed. the 8mbit sram supports low data retention voltage for battery backup operation with low data retention current. the k5c6481n(b)m is suitable for use in program and data memory of mobile communication system to reduce mount area. this device is available in 81-ball tbga type package. features power supply voltage : 2.7 to 3.0 v organization - flash : 4,194,304 x 16 bit - sram : 524,288 x 16 bit access time (@2.7v) - flash : 85 ns, sram : 55 ns power consumption - flash read current : 20 ma (typ.@5mhz) sequential page read current : 5 ma (typ.@5mhz) program/erase current : 35 ma (max.) standby mode/deep power mode : 0.1 m a (typ.) - sram operating current : 28 ma (max.) standby current : 0.5 m a (typ.) secode(security code) block : extra 32kw block (flash) block group protection / unprotection (flash) 128 words page program (flash) flash bank size : 4mb / 4mb / 28mb / 28mb sram data retention : 1.5 v (min.) industrial temperature : -40 c ~ 85 c package :81 - ball tbga type - 10.8 x 10.4 mm, 0.8 mm pitch general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. ball configuration ball description top view (ball down) a 7 u b a 8 a 3 a 6 l b c s 2 a 1 9 a 2 a 5 a 1 8 f - r y / b y a 2 0 a 9 a 4 d q 6 f - c e o e d q 9 d q 3 d q 4 d q 1 3 1 2 3 4 5 6 w e v s s a 1 0 d q 1 a 0 a 1 a 1 7 a 1 1 a 1 2 a 1 5 a 1 3 a 2 1 a 1 4 n . c a 1 6 d q 1 5 f - v c c 7 8 n . c d q 8 d q 2 d q 1 1 d q 5 d q 1 4 c s 1 d q 0 d q 1 0 v c c d q 1 2 d q 7 v s s n . c n . c n . c 9 1 0 81 ball tbga , 0.8mm pitch n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c f - w p f - r p f - v c c a b c d e f h g k j m l ball name description a 0 to a 18 address input balls (common) a 19 to a 21 address input balls (flash memory) dq 0 to dq 15 data input/output balls (common) f- rp hardware reset (flash memory) f- wp write protect (flash memory) f-vcc power supply (flash memory) vcc power supply (sram)) vss ground (common) ub upper byte enable (sram) lb lower byte enable (sram) f- ce chip enable (flash memory) cs 1 chip enable (sram low active) cs2 chip enable (sram high active) we write enable (common) oe output enable (common) f-ry/ by ready/busy (flash memory) n.c no connection 1 1 1 2 mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 3 - advance information ordering information k 5 c 64 81 n t m - t 3 5 5 samsung mcp memory device type mitsubishi nor flash + fcmos sram nor flash density (organization) , (banksize) 64 : 64mbit (x16 selectable) (4mb, 4mb, 28mb,2 8mb) block architecture t = top boot block b = bottom boot block version m = 1st generation sram access time 55 = 55 ns operating voltage range 2.7v to 3.0v package t = 81 tbga sram density , organization 8mbit , x16 selectable flash access time 3 = 85 ns mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 4 - advance information a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 f- ce oe we f- wp f- rp command user interface write state machine status/ id register y-decorder x-decorder address input chip enable output enable write enable write protect reset /powerdown main block 14 32k-word main block 8 32k-word parameter block 7 4k-word parameter block 2 4k-word boot block 1 4k-word bppt block 0 4k-word main block 22 32k-word main block 15 32k-word main block 78 32k-word main block 23 32k-word main block 134 32k-word main block 79 32k-word y-gate / sense amp. bank4 56 blocks bank3 56 blocks bank2 8 blocks bank1 15 blocks multi plexer i/o buffer dq15 dq14 dq1 dq0 data i/o 128-word page buffer f-vcc vss functional block diagram (64mbit flash memory) flash memory part mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 5 - advance information table 1. flash memory top boot block address (k5c6481nt) k5c6481nt block block size address range word mode (x16) bank4 ba134 4 kwords 3ff000h-3fffffh ba133 4 kwords 3fe000h-3fefffh ba132 4 kwords 3fd000h-3fdfffh ba131 4 kwords 3fc000h-3fcfffh ba130 4 kwords 3fb000h-3fbfffh ba129 4 kwords 3fa000h-3fafffh ba128 4 kwords 3f9000h-3f9fffh ba127 4 kwords 3f8000h-3f8fffh ba126 32 kwords 3f0000h-3f7fffh ba125 32 kwords 3e8000h-3effffh ba124 32 kwords 3e0000h-3e7fffh ba123 32 kwords 3d8000h-3dffffh ba122 32 kwords 3d0000h-3d7fffh ba121 32 kwords 3c8000h-3cffffh ba120 32 kwords 3c0000h-3c7fffh bank3 ba119 32 kwords 3b8000h-3bffffh ba118 32 kwords 3b0000h-3b7fffh ba117 32 kwords 3a8000h-3affffh ba116 32 kwords 3a0000h-3a7fffh ba115 32 kwords 398000h-39ffffh ba114 32 kwords 390000h-397fffh ba113 32 kwords 388000h-38ffffh ba112 32 kwords 380000h-387fffh bank2 ba111 32 kwords 378000h-37ffffh ba110 32 kwords 370000h-377fffh ba109 32 kwords 368000h-36ffffh ba108 32 kwords 360000h-367fffh ba107 32 kwords 358000h-35ffffh ba106 32 kwords 350000h-357fffh ba105 32 kwords 348000h-34ffffh ba104 32 kwords 340000h-347fffh ba103 32 kwords 338000h-33ffffh ba102 32 kwords 330000h-337fffh ba101 32 kwords 328000h-32ffffh ba100 32 kwords 320000h-327fffh ba99 32 kwords 318000h-31ffffh ba98 32 kwords 310000h-317fffh ba97 32 kwords 208000h-20ffffh ba96 32 kwords 300000h-307fffh ba95 32 kwords 2f8000h-2fffffh ba94 32 kwords 2f0000h-2f7fffh ba93 32 kwords 2e8000h-2effffh ba92 32 kwords 2e0000h-2e7fffh ba91 32 kwords 2d8000h-2dffffh ba90 32 kwords 2d0000h-2d7fffh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 6 - advance information table 1. flash memory top boot block address (k5c6481nt) k5c6481nt block block size address range word mode (x16) bank2 ba89 32 kwords 2c8000h-2cffffh ba88 32 kwords 2c0000h-2c7fffh ba87 32 kwords 2b8000h-2bffffh ba86 32 kwords 2b0000h-2b7fffh ba85 32 kwords 2a8000h-2affffh ba84 32 kwords 2a0000h-2a7fffh ba83 32 kwords 298000h-29ffffh ba82 32 kwords 290000h-297fffh ba81 32 kwords 288000h-28ffffh ba80 32 kwords 280000h-287fffh ba79 32 kwords 278000h-27ffffh ba78 32 kwords 270000h-277fffh ba77 32 kwords 268000h-26ffffh ba76 32 kwords 260000h-267fffh ba75 32 kwords 258000h-25ffffh ba74 32 kwords 250000h-257fffh ba73 32 kwords 248000h-24ffffh ba72 32 kwords 240000h-247fffh ba71 32 kwords 238000h-23ffffh ba70 32 kwords 230000h-237fffh ba69 32 kwords 228000h-22ffffh ba68 32 kwords 220000h-227fffh ba67 32 kwords 218000h-21ffffh ba66 32 kwords 210000h-217fffh ba65 32 kwords 208000h-20ffffh ba64 32 kwords 200000h-207fffh ba63 32 kwords 1f8000h-1fffffh ba62 32 kwords 1f0000h-1f7fffh ba61 32 kwords 1e8000h-1effffh ba60 32 kwords 1e0000h-1e7fffh ba59 32 kwords 1d8000h-1dffffh ba58 32 kwords 1d0000h-1d7fffh ba57 32 kwords 1c8000h-1cffffh ba56 32 kwords 1c0000h-1c7fffh bank1 ba55 32 kwords 1b8000h-1bffffh ba54 32 kwords 1b0000h-1b7fffh ba53 32 kwords 1a8000h-1affffh ba52 32 kwords 1a0000h-1a7fffh ba51 32 kwords 198000h-19ffffh ba50 32 kwords 190000h-197fffh ba49 32 kwords 188000h-18ffffh ba48 32 kwords 180000h-187fffh ba47 32 kwords 178000h-17ffffh ba46 32 kwords 170000h-177fffh ba45 32 kwords 168000h-16ffffh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 7 - advance information table 1. flash memory top boot block address (k5c6481nt) k5c6481nt block block size address range word mode (x16) bank1 ba44 32 kwords 160000h-167fffh ba43 32 kwords 158000h-15ffffh ba42 32 kwords 150000h-157fffh ba41 32 kwords 148000h-14ffffh ba40 32 kwords 140000h-147fffh ba39 32 kwords 138000h-13ffffh ba38 32 kwords 130000h-137fffh ba37 32 kwords 128000h-12ffffh ba36 32 kwords 120000h-127fffh ba35 32 kwords 118000h-11ffffh ba34 32 kwords 110000h-117fffh ba33 32 kwords 108000h-10ffffh ba32 32 kwords 100000h-107fffh ba31 32 kwords f8000h-fffffh ba30 32 kwords f0000h-f7fffh ba29 32 kwords e8000h-effffh ba28 32 kwords e0000h-e7fffh ba27 32 kwords d8000h-dffffh ba26 32 kwords d0000h-d7fffh ba25 32 kwords c8000h-cffffh ba24 32 kwords c0000h-c7fffh ba23 32 kwords b8000h-bffffh ba22 32 kwords b0000h-b7fffh ba21 32 kwords a8000h-affffh ba20 32 kwords a0000h-a7fffh ba19 32 kwords 98000h-9ffffh ba18 32 kwords 90000h-97fffh ba17 32 kwords 88000h-8ffffh ba16 32 kwords 80000h-87fffh ba15 32 kwords 78000h-7ffffh ba14 32 kwords 70000h-77fffh ba13 32 kwords 68000h-6ffffh ba12 32 kwords 60000h-67fffh ba11 32 kwords 58000h-5ffffh ba10 32 kwords 50000h-57fffh ba9 32 kwords 48000h-4ffffh ba8 32 kwords 40000h-47fffh ba7 32 kwords 38000h-3ffffh ba6 32 kwords 30000h-37fffh ba5 32 kwords 28000h-2ffffh ba4 32 kwords 20000h-27fffh ba3 32 kwords 18000h-1ffffh ba2 32 kwords 10000h-17fffh ba1 32 kwords 08000h-0ffffh ba0 32 kwords 00000h-07fffh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 8 - advance information table 2. flash memory bottom boot block address (k5c6481nb) k5c6481nb block block size address range word mode (x16) bank4 ba134 32 kwords 3f8000h-3fffffh ba133 32 kwords 3f0000h-3f7fffh ba132 32 kwords 3e8000h-3effffh ba131 32 kwords 3e0000h-3e7fffh ba130 32 kwords 3d8000h-3dffffh ba129 32 kwords 3d0000h-3d7fffh ba128 32 kwords 3c8000h-3cffffh ba127 32 kwords 3c0000h-3c7fffh ba126 32 kwords 3b8000h-3bffffh ba125 32 kwords 3b0000h-3b7fffh ba124 32 kwords 3a8000h-3affffh ba123 32 kwords 3a0000h-3a7fffh ba122 32 kwords 398000h-39ffffh ba121 32 kwords 390000h-397fffh ba120 32 kwords 388000h-38ffffh ba119 32 kwords 380000h-387fffh ba118 32 kwords 378000h-37ffffh ba117 32 kwords 370000h-377fffh ba116 32 kwords 368000h-36ffffh ba115 32 kwords 360000h-367fffh ba114 32 kwords 358000h-35ffffh ba113 32 kwords 350000h-357fffh ba112 32 kwords 348000h-34ffffh ba111 32 kwords 340000h-347fffh ba110 32 kwords 338000h-33ffffh ba109 32 kwords 330000h-337fffh ba108 32 kwords 328000h-32ffffh ba107 32 kwords 320000h-327fffh ba106 32 kwords 318000h-31ffffh ba105 32 kwords 310000h-317fffh ba104 32 kwords 208000h-20ffffh ba103 32 kwords 300000h-307fffh ba102 32 kwords 2f8000h-2fffffh ba101 32 kwords 2f0000h-2f7fffh ba100 32 kwords 2e8000h-2effffh ba99 32 kwords 2e0000h-2e7fffh ba98 32 kwords 2d8000h-2dffffh ba97 32 kwords 2d0000h-2d7fffh ba96 32 kwords 2c8000h-2cffffh ba95 32 kwords 2c0000h-2c7fffh ba94 32 kwords 2b8000h-2bffffh ba93 32 kwords 2b0000h-2b7fffh ba92 32 kwords 2a8000h-2affffh ba91 32 kwords 2a0000h-2a7fffh ba90 32 kwords 298000h-29ffffh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 9 - advance information table 2. flash memory bottom boot block address (k5c6481nb) k5c6481nb block block size address range word mode (x16) bank4 ba89 32 kwords 290000h-297fffh ba88 32 kwords 288000h-28ffffh ba87 32 kwords 280000h-287fffh ba86 32 kwords 278000h-27ffffh ba85 32 kwords 270000h-277fffh ba84 32 kwords 268000h-26ffffh ba83 32 kwords 260000h-267fffh ba82 32 kwords 258000h-25ffffh ba81 32 kwords 250000h-257fffh ba80 32 kwords 248000h-24ffffh ba79 32 kwords 240000h-247fffh bank3 ba78 32 kwords 238000h-23ffffh ba77 32 kwords 230000h-237fffh ba76 32 kwords 228000h-22ffffh ba75 32 kwords 220000h-227fffh ba74 32 kwords 218000h-21ffffh ba73 32 kwords 210000h-217fffh ba72 32 kwords 208000h-20ffffh ba71 32 kwords 200000h-207fffh ba70 32 kwords 1f8000h-1fffffh ba69 32 kwords 1f0000h-1f7fffh ba68 32 kwords 1e8000h-1effffh ba67 32 kwords 1e0000h-1e7fffh ba66 32 kwords 1d8000h-1dffffh ba65 32 kwords 1d0000h-1d7fffh ba64 32 kwords 1c8000h-1cffffh ba63 32 kwords 1c0000h-1c7fffh ba62 32 kwords 1b8000h-1bffffh ba61 32 kwords 1b0000h-1b7fffh ba60 32 kwords 1a8000h-1affffh ba59 32 kwords 1a0000h-1a7fffh ba58 32 kwords 198000h-19ffffh ba57 32 kwords 190000h-197fffh ba56 32 kwords 188000h-18ffffh ba55 32 kwords 180000h-187fffh ba54 32 kwords 178000h-17ffffh ba53 32 kwords 170000h-177fffh ba52 32 kwords 168000h-16ffffh ba51 32 kwords 160000h-167fffh ba50 32 kwords 158000h-15ffffh ba49 32 kwords 150000h-157fffh ba48 32 kwords 148000h-14ffffh ba47 32 kwords 140000h-147fffh ba46 32 kwords 138000h-13ffffh ba45 32 kwords 130000h-137fffh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 10 - advance information table 2. flash memory bottom boot block address (k5c6481nb) k5c6481nb block block size address range word mode (x16) bank3 ba44 32 kwords 128000h-12ffffh ba43 32 kwords 120000h-127fffh ba42 32 kwords 118000h-11ffffh ba41 32 kwords 110000h-117fffh ba40 32 kwords 108000h-10ffffh ba39 32 kwords 100000h-107fffh ba38 32 kwords f8000h-fffffh ba37 32 kwords f0000h-f7fffh ba36 32 kwords e8000h-effffh ba35 32 kwords e0000h-e7fffh ba34 32 kwords d8000h-dffffh ba33 32 kwords d0000h-d7fffh ba32 32 kwords c8000h-cffffh ba31 32 kwords c0000h-c7fffh ba30 32 kwords b8000h-bffffh ba29 32 kwords b0000h-b7fffh ba28 32 kwords a8000h-affffh ba27 32 kwords a0000h-a7fffh ba26 32 kwords 98000h-9ffffh ba25 32 kwords 90000h-97fffh ba24 32 kwords 88000h-8ffffh ba23 32 kwords 80000h-87fffh bank2 ba22 32 kwords 78000h-7ffffh ba21 32 kwords 70000h-77fffh ba20 32 kwords 68000h-6ffffh ba19 32 kwords 60000h-67fffh ba18 32 kwords 58000h-5ffffh ba17 32 kwords 50000h-57fffh ba16 32 kwords 48000h-4ffffh ba15 32 kwords 40000h-47fffh bank1 ba14 32 kwords 38000h-3ffffh ba13 32 kwords 30000h-37fffh ba12 32 kwords 28000h-2ffffh ba11 32 kwords 20000h-27fffh ba10 32 kwords 18000h-1ffffh ba9 32 kwords 10000h-17fffh ba8 32 kwords 08000h-0ffffh ba7 4 kwords 07000h-07fffh ba6 4 kwords 06000h-06fffh ba5 4 kwords 05000h-05fffh ba4 4 kwords 04000h-04fffh ba3 4 kwords 03000h-03fffh ba2 4 kwords 02000h-02fffh ba1 4 kwords 01000h-01fffh ba0 4 kwords 00000h-00fffh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 11 - advance information flash memory command definition table 3. command list (f- wp = v ih or v il ) notes : 1. upper byte data (dq15-dq8) is ignored. 2. bank=bank address (bank1-bank4:a21-18) 3. ia=id code address:a0=v il (manufacture?s code):a0=v ih (device code), id=id code 4. srd=status register data 5. sa=sequential page address:a21-a3, a2-a0:0h 6. sa+i;a21-a3 must be flxed and a2-a0 must be incremented from 0h to 7h. command 1st cycle 2nd cycle 3rd cycle mode address data 1) (dq0-15) mode address data 1) (dq0-15) mode address data 1) (dq0-15) a21-a18 a0 read array write x ffh sequential page read write x f3h read sa 5) rd0 read sa+i 6) rdi device identifier write bank 2) 90h read bank 2) ia 3) id read status register write bank 2) 70h read bank 2) srd 4) clear status register write x 50h suspend write bank 2) b0h resume write bank 2) d0h table 4. command list (f- wp = v ih ) notes : 1. upper byte data (dq15-dq8) is ignored. 2. wa=write address, wd=write data 3. wa0, wan=write address, wd0, wdn=write data, write address and write data must be provided sequentially from 00h to 7fh for a6-a0. page size is 128 words (128-word x 16-bit), and also a21-a7(block address, page address) must be valid. 4. wa=write address:a21-a7 (block address, page address) must be valid. 5. ba=block address:a21-a12(bank1), a21-a15(bank2, bank3, bank4) 6. ra=read address:a21-a7 (block address, page address) must be valid. command 1st cycle 2nd cycle 3rd cycle mode address data 1) (dq0-15) mode address data 1) (dq0-15) mode address data 1) (dq0-15) word program write bank 40h write wa 2) wd 2) page program write bank 41h write wa0 3) wd0 3) write wan 3) wdn 3) page buffer to flash write bank 0eh write wa 4) d0 1) block erase / confirm write bank 20h write ba 5) d0 1) erase all unlocked blocks write x a7h write x d0 1) clear page buffer write x 55h write x d0 1) single date load to page buffer write bank 74h write wa wd flash to page buffer write bank f1h write ra 6) d0 1) mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 12 - advance information flash memory command definition software lock release operation needs following consecutive 7bus cycles. moreover, additional 127 bus cycles are needed for page program operation. table 5. command list (f- wp = v ih or v il ) setup command for software lock release 1st cycle 2nd cycle 3rd cycle mode address data 1) (dq0-15) mode address data 1) (dq0-15) mode address data 1) (dq0-15) word program write bank 60h write bank block 6) write bank ach page program 3) write bank 60h write bank block 6) write bank ach page buffer to flash write bank 60h write bank block 6) write bank ach block erase / confirm write bank 60h write bank block 6) write bank ach erase all unlocked blocks write bank 60h write bank block 6) write bank ach clear page buffer write bank 60h write bank block 6) write bank ach single data load to page buffer write bank 60h write bank block 6) write bank ach flash to page buffer write bank 60h write bank block 6) write bank ach setup command for software lock release 4th cycle 5th cycle mode address data 1) (dq0-15) mode address data 1) (dq0-15) word program write bank block 6) write bank 78h page program 3) write bank block 6) write bank 78h page buffer to flash write bank block 6) write bank 78h block erase / confirm write bank block 6) write bank 78h erase all unlocked blocks write bank block 6) write bank 78h clear page buffer write bank block 6) write bank 78h single data load to page buffer write bank block 6) write bank 78h flash to page buffer write bank block 6) write bank 78h notes : 1. upper byte data (dq15-dq8) is ignored. 2. wa=write address, wd=write data 3. wa0, wan=write address, wd0, wdn=write data, write address and write data must be provided sequentially from 00h to 7fh for a6-a0. page size is 128 words (128 word x 16 bit), and also a21-a7(block address, page address) must be valid. 4. wa=write address:a21-a7 (block address, page address) must be valid. 5. ba=block address:a21-a12(bank1), a21-a15(bank2, bank3, bank4) 6. block=block address:a21-a15, block = a21 - a15 setup command for software lock release 6th cycle 7th cycle 8th-134th cycle mode address data 1) (dq0-15) mode address data 1) (dq0-15) mode address data 1) (dq0-15) word program write bank 40h write wa 2) wd 2) page program 3) write bank 41h write wa0 3) wd0 3) write wan 3) wdn 3) page buffer to flash write bank 0eh write wa 4) d0 1) block erase / confirm write bank 20h write ba 5) d0 1) erase all unlocked blocks write x a7h write x d0 1) clear page buffer write x 55h write x d0 1) single data load to page buffer write bank 74h write wa wd flash to page buffer write bank f1h write ra 7) d0 1) address dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 block fixed0 a21 a20 a19 a18 a17 a16 a15 block fixed0 a21 a20 a19 a18 a17 a16 a15 7. ra=read address: a21-a7 (block address, page address) must be valid. mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 13 - advance information table 6. device id code the output of upper byte data (dq15-dq7) is "0". code \ pins a0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex date manufacturer code v il "0" "0" "0" "1" "1" "1" "0" "0" 1ch devide code (bottom boot) v ih "0" "0" "1" "0" "1" "0" "1" "0" 2ah devide code (top boot) v ih "0" "0" "1" "0" "1" "0" "1" "1" 2bh table 7. block locking f- wp pin must not be switched during performing read / write operations or wsm busy (wsms=0). f- rp f- wp write protection provided notes bank1 bank2 bank3 bank4 boot parameter/main main main main v il x locked locked locked locked locked deep power down mode v ih v il locked locked locked locked locked all blocks locked (valid to operate software lock release) v ih unlocked unlocked unlocked unlocked unlocked all blocks unlocked table 8. status register symbol (i/o pin) status definition "1" "0" s.r.7 (aq7) write state machine status ready busy s.r.6 (dq6) suspend status suspended operation in progress/completed s.r.5 (dq5) erase status error successful s.r.4 (dq4) program status error successful s.r.3 (dq3) block status after program error successful s.r.2 (dq2) reserved - - s.r.1 (dq1) reserved - - s.r.0 (dq0) reserved - - table 9. flash memory operation table notes : 1. x cab be v ih or v il for control pins mode \ pins f- ce oe we f- rp dq0-15 read array v il v il v ih v ih data-output sequential v il v il v ih v ih data-output status register v il v il v ih v ih status register data identifier code v il v il v ih v ih identifier code output disable v il v ih v ih v ih high-z write program v il v ih v il v ih command / data-in erase v il v ih v il v ih command others v il v ih v il v ih command standby v ih x 1) x v ih high-z deep power down x x x v il high-z mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 14 - advance information flash device operation the 64mbit dinor iv flash memory includes on-chip program/erase control circuitry. the write state machine(wsm) control block erase and word/page program operations. operational modes are selected by the commands written to the command user inter- face (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep power down mode is enabled when the f- rp pin is at vss, minimizing power consumption. read mode the 64mbit dinor iv flash memory has four read modes, which accesses to the memory array, the sequential page read, the device identifier and the status register. the appropriate read commands are required to be written to the cui. upon initial dev ice power up or after exit from deep power down, the 64mbit dinor iv flash memory automatically resets to read array mode. in the read array mode and in the conditions are low level input to oe , high level input to we and f- rp , low level input to f- ce and address signals to the address inputs (a21 - a0) the data of the addressed location to the data input/output (dq15-dq0) is outpu t. standby mode when f- ce is at v ih , the device is in the standby mode and its power consumption is reduced. data input/output are in a high- impedance (high-z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consumes normal active power until the operation completes. output disable when oe is at v ih , output from the devices is disabled. data input/output are in a high-impedance (high-z) state. automatic power down (apd) the automatic power down minimizes the power consumption during read mode. the device automatically turns to this mode when any addresses or f- ce isn't changed more than 200ns after the last alternation. the power consumption becomes the same as the stand-by mode. during this mode, the output data is latched and can be read out. new data is read out correctly when addresses are changed. deep power down when f- rp is at v il , the device is in the deep power down mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high-impedance (high-z) state. after return from power down, the cui is reset to read array, and the status register is cleared to value 80h. during block erase or program modes, f- rp low will abort either operation. memory array data of the block being altered become invalid. write mode writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing we to low level and oe is at high level, while f- ce is at low level. address and data are latched on the earlier rising edge of we and f- ce . standard micro processor write timings are used. alternating background operation (bgo) the 64mbit dinor iv flash memory allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. array read operation with the other bank in bgo is performed b y changing the bank address without any additional command. when the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. the access time with bgo is the s ame as the normal read operation. bgo must be between bank1, bank2, bank3, and bank4. back bank array read (bbr) in the 64mbit dinor iv flash memory , when one memory address is read according to a read mode in the case of the same as an access when a read mode command is input, an another bank memory data can be read out (random or sequential mode) by changing an another bank address. mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 15 - advance information software command definitions tthe device operations are selected by writing specific software command into the commnad user interface. read array command (ffh) the device is in read array mode on initial device power up and after exit from deep power down, or by writing ffh to the com- mand user interface. after starting the internal operation the device is set to the read status register mode automatically. sequential page read command (f3h) the sequential page read command (f3h) timing can be used by writing the first command. this command is fast sequential 8 words read. during the read it is necessary to fix f- ce low and increase the addresses sequentially from 0h to 7h. the mode is kept until read array command is input. the first read of seq. page read timing is the same as normal read (ta(ce)). f- ce should be fallen ?l?. the read timing after the first is fast read (ta(pad)). when an another sequential page (a21-a3) is accessed before one sequential page (one 8-word) read is not finished, once f- ce is at v ih and a2-a0 data are 0h, after that f- ce is at v il we can use the first read of seq. page read or normal read (ta(ce)). read device indentifier command (90h) we can normally read device identifier codes when read device identifier code command (90h) is written to the command latch. following the command write, the manufacturer code and the device code can be read from address 0000h and 0001h, respec- tively. read status register command (70h) the status register is read after writing the read status register command of 70h to the command user interface. also, after starting the internal operation the device is set to the read status register mode automatically. the contents of status registe r are latched on the later falling edge of oe must be toggled every status read. clear status register command (50h) the erase status, program status and block status bits are set to "1"s by the write state machine and can only be reset by the clear status register command of 50h. these bits indicate various failure conditions. status read. block erase / confirm command (20h/d0h) automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation . program commands 1) word program (40h) word program is executed by a two-command sequence. the word program setup command of 40h is written to the command interface, followed by a second write specifying the address and data to be written. the wsm controls the program pulse applicat ion and verify operation. 2) page program for data blocks (41h) page program allows fast programming of 128words of data. writing of 41h initiates the page program operation for the data area. from 2nd cycle to 129th cycle, write data must be serially inputted. address a6-a0 have to be incremented from 00h to 7fh. after completion of data loading, the wsm controls the program pulse application and verify operation. 3) single data load to page buffer (74h) / page buffer to flash (0eh/d0h) single data load to the page buffer is performed by writing 74h followed by a second write specifying the column address and dat a. distinct data up to 128word can be loaded to the page buffer by this two-command sequence. on the other hand, all of the loaded data to the page buffer is programmed simultaneously by writing page buffer to flash command of 0eh followed by the confirm command of d0h. after completion of programming the data on the page buffer is cleared automatically. mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 16 - advance information flash to page buffer command (f1h/d0h) array data load to the page buffer is performed by writing the flash to page buffer command of f1h followed by the confirm com- mand of d0h. an address within the page to be loaded is required. then the array data can be copied into the other pages within the same bank by using the page buffer to flash command. clear page buffer command (55h/d0h) loaded data to the page buffer is cleared by writing the clear page buffer command of 55h followed by the confirm command of d0h. this command is valid for clearing data loaded by single data load to page buffer command. suspend/resume command (b0h/d0h) writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the bank address is required when writing the suspend/resume command. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status an d suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of t he read array command to the cui enables reading data from blocks other than that which is suspended. when the resume com- mand of d0h is written to the cui, the wsm will continue with the erase or program processes. data protection the 64m-bit dinor(iv) flash memory has a master write protect pin (f- wp ). when f- wp is at v ih , all blocks can be programmed or erased. when f- wp is low, all blocks are in locked mode which prevents any modifications to memory blocks. software lock release function is only command which allows to program or erase. see the block locking table on 13 page for details. power supply voltage when the power supply voltage is less than v lko , low vcc lock-out voltage, the device is set to the read-only mode. regarding dc electrical characteristics of v lko , see 18 page. a delay time of 2us is required before any device operation is initiated. the delay time is measured from the time vcc reaches vccmin (2.7v). during power up, f- rp = vss is recommended. falling in busy status is not recommended for possibility of damaging the device. memory organization the 64mbit dinor iv flash memory is constructed by 2 boot blocks of 4k words, 6 parameter blocks of 4k words and 7 main blocks of 32k words in bank1, by 8 main blocks of 32k words in bank2 and by 56 main blocks of 32k words in bank3 and bank4. capacitance item symbol test condition min max unit input capacitance a21-a0, oe , we , cs2. f- ce , f- wp , f -rp c in ta=25 c, f=1mhz, vin=vout=0v 8 pf output capacitance dq15-dq0, f-ry/ by c out 12 pf mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 17 - advance information absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input / output pins. during transitions, the level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input / output pins is f-vcc+0.5v which, during transitions, may overshoot to f-vcc+1.5v f or periods <20ns. parameter symbol conditions rating unit f-vcc voltage f-vcc with respect to vss -0.2 to +4.6 v all input or output voltage 1) vi1 -0.6 to +4.6 ambient temperature ta -20 to +85 c temperature under bias tbs -50 to +95 storage temperature tstg -65 to +125 outputs short circuit current iout 100 (max.) ma notes : all currents are in rms unless otherwise noted 1. typical values at f-vcc=2.85v, ta=25 c . 2. to protect initiation of write cycle during f-vcc power up / down, a write cycle is locked out for f-vcc less than v lko , write state machine is in busy state, if f-vcc is less than v lko , the alteration of memory contents may occur. parameter sym- bol test conditions min typ 1) max unit input leakage current i li 0v mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 19 - advance information ac characteristics read / write mode ( ce control) notes : 1. timing measurements are made under ac waveforms for read operations 2. typical values at f-vcc=2.85v and ta=25 c. parameter symbol vcc=2.7v~3.0v unit min typ max write cycle time twc tavav 85 ns address setup time tas tavwh 35 ns address hold time tah twhax 0 ns data setup time tds tdvwh 35 ns data hold time tdh twhdx 0 ns oe hold from we high toeh twhgl 10 ns write enable setup time tws twlel 0 ns write enable hold time twh tehwh 0 ns f- ce pulse width tcep teleh 35 ns f- ce "h" pulse width tceph tehel 30 ns oe hold to we low tghel tghel 85 ns block lock setup to write enable high tbls tphhwh 85 ns block lock hold from valid srd tblh tqvph 0 ns duration of auto program operation (word mode) tdap twhrh1 30 300 m s duration of auto program operation (page mode) tdap twhrh1 4 80 ms duration of auto block erase operation tdae twhrh2 150 600 ms delay time to begin internal operation tehrl tehrl 90 ns f- rp recovery to f- ce low tps tphwl 150 ns program / erase time parameter min typ max unit block erase time 150 600 ms main block write time 1 4 sec page write time 4 80 ms flash to page buffer time 100 150 m s program suspend / erase suspend time parameter min typ max unit program suspend time 15 m s erase suspend time 15 m s f-vcc power up / down timing please see 21 page. during power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. the device must be protected against initiation of write cycle for memory contents during power up / down. the delay time of min. 2 micro sec is al ways required before read operation or write operation is initiated from the time f-vcc reaches f-vcc min. during power up /down. by holding f - rp =v il , the contents of memory is protected during f-vcc power up / down. during power up, f- rp must be held v il for min. 2us form the time f-vcc reaches f-vcc min.. during power down, f- rp must be held v il until f-vcc reaches vss. f- rp doesn?t have latch mode, therefore f- rp must be held v ih during read operation or erase / program operation. parameter min typ max unit tvcs f-rp=v ih setup time from f-vcc min. 2 15 m s mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 20 - advance information v cc f- rp we f- ce f-vcc power up / dowm timing t vcs read /write inhibit v ih v il 2.85v vss v ih v il v ih v il read /write inhibit read /write inhibit t ps t ps ac waveforms for read operation and test conditions t a(ad) address t rc t a(ce) t df(ce) t oeh t df(oe) t a(oe) t olz t clz high-z high-z t oh t phz t ps address oe f- ce v ih v il v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il test conditions for ac characteristics input voltage: v il =0v, v ih =flash v cc input rise and fall times: 5ns reference voltage at timing measurement: (flash v cc )/2 output load: 1ttl gate + cl(30pf) or dut 1.3v 1n914 3.3kohm mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 21 - advance information ac waveforms for sequential page read operation a 21 ~ a 3 f- ce a 2 ~ a 0 v ih v il v ih v il v ih v il oe data we v ih v il v ih v il v ih v il t a(pad) address address address 1h 0h 2h 4h 5h 3h 6h 7h dout valid valid valid valid valid valid valid t a(pad) t a(pad) t a(pad) t a(pad) t a(pad) t a(pad) t a(ad) t a(ce) f3h high-z address mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 22 - advance information ac waveforms for word program operation( we control) a 21 ~ a 0 oe f- ce v ih v il v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il bank address t wc 40h din sr ffh valid address vaild bank address write read register program f- wp v ih v il address t as t ah t cs t ch t a(ce) t a(oe) t wp t wph t oeh t ds t whrl t ps t bls t dap t blh busy sr ready t dh ac waveforms for word program operation( ce control) a 21 ~ a 0 oe f- ce v ih v il v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il bank address t wc 40h din sr ffh valid address vaild bank address valid write read register program f- wp v ih v il address t as t ah t a(ce) t a(oe) t cep t wh t oeh t ds t ehrl t ps t bls t dap t blh busy sr ready t dh t ws read status register read status register high-z high-z mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 23 - advance information ac waveforms for page program operation( we control) a 21 ~ a 7 oe f- ce v ih v il v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il f- wp v ih v il address t wc write read register read status register 00h 7fh din dou din din sr busy sr ready ffh the other bank vaild address vaild address vaild bank address address vaild bank address vaild vaild 01h-7eh t as t ah t a(oe) t cs t ch t a(ce) t a(ce) t wp t wph t oeh t a(oe) t ghwl t oeh t dh high-z t ds 41h t dap t whrl t blh t bls v ih v il a 6 ~ a 0 ac waveforms for page program operation( ce control) a 21 ~ a 7 oe f- ce v ih v il v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il f- wp v ih v il address t wc write read register read status register 00h 7fh din dou din din sr busy sr ready ffh the other bank vaild address vaild address vaild bank address address vaild bank address vaild vaild 01h-7eh t as t ah t a(oe) t ws t wh t a(ce) t a(ce) t cep t ceph t oeh t a(oe) t ghwl t oeh t dh high-z t ds 41h t dap t ehrl t blh t bls v ih v il a 6 ~ a 0 t ps mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 24 - advance information ac waveforms for erase operation( we control) a 21 ~ a 0 oe f- ce v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il f- wp v ih v il address write read register read status register bank address t blh t wc v ih v il vaild bank address address vaild 20h doh ffh erase t as t ah t cs t ch t a(ce) t wp t wph t oeh t a(oe) t ds t whrl t ps t dh t bls t dae sr busy sr ready ac waveforms for erase operation( ce control) a 21 ~ a 0 oe f- ce v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il f- wp v ih v il address write read register read status register bank address t blh t wc v ih v il vaild bank address address vaild 20h doh ffh erase t as t ah t ws t wh t a(ce) t cep t oeh t a(oe) t ds t whrl t ps t dh t bls t dae sr busy sr ready high-z high-z mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 25 - advance information ac waveforms for word program operation with bgo( we control) a 21 ~ a 7 oe f- ce v ih v il v ih v il v ih v il we data v ih v il v ih v il v ih v il address read array in another bank vaild bank address address vaild a 6 ~ a 0 t wc t as t ah t a(ce) address vaild address vaild address vaild address vaild din high-z 40h change bank address read status register program in one bank address vaild sr busy dout dout t cs t ch t wp t wph t oeh t a(oe) t ds t whrl t dh ac waveforms for word program operation with bgo( ce control) a 21 ~ a 7 oe f- ce v ih v il v ih v il v ih v il we data v ih v il v ih v il v ih v il address read array in another bank vaild bank address address vaild a 6 ~ a 0 t wc t as t ah t a(ce) address vaild address vaild address vaild address vaild din high-z 40h change bank address read status register program in one bank address vaild sr busy dout dout t ws t cep t oeh t a(oe) t ds t ehrl t dh t wh program program mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 26 - advance information ac waveforms for page program operatio with bgo( we control) a 21 ~ a 7 oe f- ce v ih v il v ih v il v ih v il we data v ih v il v ih v il v ih v il address read array in another bank vaild bank address address vaild a 6 ~ a 0 t wc t as t ah address vaild address vaild address vaild address vaild change bank address program in one bank 00h 01h-7eh din high-z 41h dout t ds din din dout valid 7fh t a(ce) t a(oe) t a(ce) t cs t ch t wp t wph t oeh t a(oe) t ghwl t oeh t whrl t dh dou sr busy ac waveforms for page program operatio with bgo( ce control) a 21 ~ a 7 oe f- ce v ih v il v ih v il v ih v il we data v ih v il v ih v il v ih v il address read array in another bank vaild bank address address vaild a 6 ~ a 0 t wc t as t ah address vaild address vaild change bank address program in one bank 00h 01h-7eh din high-z dout t ds din din dout valid 7fh t a(ce) t a(oe) t a(ce) t ws t wh t cep t a(oe) t ghel t oeh t ehrl t dh dout sr busy t ceph t ehrl 41h mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 27 - advance information ac waveforms for erase operation with bgo( we control) a 21 ~ a 0 oe f- ce v ih v il v ih v il we data v ih v il v ih v il v ih v il address address vaild t wc vaild bank address 20h doh t as t cs t ch t a(ce) t wp t wph t oeh t a(oe) t ds t whrl t dh sr busy high-z address vaild address vaild t ah dout dout read array in another bank change bank address read status register program in one bank a 21 ~ a 0 oe f- ce v ih v il v ih v il we data v ih v il v ih v il v ih v il address t wc vaild bank address 20h doh t as t ws t wh t a(ce) t cep t oeh t a(oe) t ds t ehrl t dh sr busy high-z ac waveforms for erase operation with bgo( ce control) address vaild address vaild address vaild read array in another bank change bank address read status register program in one bank t ah dout dout mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 28 - advance information ac waveforms for suspend operation( we control) bank address vaild t bls t cs t ch t a(ce) t wp t oeh s.r.6,7=1 sr busy high-z t ah read status register t as b0h t a(oe) suspend time t blh bank address vaild a 21 ~ a 0 oe f- ce v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il f- wp v ih v il address v ih v il ac waveforms for suspend operation( ce control) bank address vaild t bls t ws t a(ce) t cep s.r.6,7=1 sr busy high-z t ah read status register t as b0h t a(oe) suspend time t blh bank address vaild a 21 ~ a 0 oe f- ce v ih v il v ih v il we f- rp data v ih v il v ih v il v ih v il f- wp v ih v il address v ih v il t oeh t wh mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 29 - advance information sr.7=1? start write 40h word program flow chart write address, data status register read full status check if desired word program completed suspend loop write d0h yes no no yes n=7fh? start write 41h page program flow chart status register read page program completed suspend loop write d0h write yes no no yes n = 0 write address n, data n sr.7=1? full status check if desired boh? yes n = 0 no yes sr.7=1? start write 20h block erase flow chart write d0h block address status register read full status check if desired erase completed suspend loop write d0h write yes no no yes boh? sr.4,5=1? start status register check flow chart pass (block erase, program) yes command sequence error sr.5=0? no block erase error no sr.4=0? no program error (page program) yes sr.3=0? no block erase error (block fail) yes yes yes yes write boh? mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 30 - advance information load start write 74h single data load to page buffer write address, data single data load to page buffer no s.r.6=1? start write b0h suspend / resume flow chart write ffh operation restart status register read read write d0h yes yes sr.7=1? start write 0h page buffer to flash flow chart write d0h page address status register read full status check if desired suspend loop write d0h write yes no no yes boh? s.r.7=1? no erase/program finished flow chart completed finished? yes page buffer to flash completed read array data yes finished? no suspend resume start write 55h clear page buffer flow chart clear page buffer completed write d0h no mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 31 - advance information operation status ( wp =v ih ) single data load to page bufer setup clear page bufer setup flash page burrer setup page buffer to flash setup page program setup word program setup block erase setup erase all unlocked blocks setup read status register program & read device identifier read/standby state (read array mode) read/standby state (sequential page read mode) ffh (read array) f3h (seq. page) 70h 70h 90h 90h ffh (read array) f3h (seq. page) clear status register 50h seq. page read read array (from the other bank) change bank address d0h wd d0h 55h f1h 74h 0eh 41h 40h 20h a7h setup state verift read status register erase & verift read status register read status register read array seq. page read read array (from the other bank) change bank address change bank address b0h b0h d0h d0h d0h wd d0h d0h other wdi i=0-127 other ffh (read array) f3h (seq. page) 70h read state with bgo internal state ffh f3h suspend state read array ready mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 32 - advance information operation status ( wp =v il ) single data load to page bufer setup clear page bufer setup flash page burrer setup page buffer to flash setup page program setup word program setup block erase setup erase all unlocked blocks setup program & d0h wd d0h 55h f1h 74h 0eh 41h 40h 20h a7h setup state verift read status register erase & verift read status register read status register read array seq. page read read array (from the other bank) change bank address change bank address b0h b0h d0h d0h d0h wd d0h d0h wdi i=0-127 ready ffh (read array) f3h (seq. page) 70h read state with bgo internal state suspend state read status register read device identifier read/standby state (read array mode) read/standby state (sequential page read mode) ffh (read array) f3h (seq. page) 70h 70h 90h 90h ffh (read array) f3h (seq. page) ffh f3h read array clear status register 50h seq. page read read array (from the other bank) change bank address single data load to page bufer setup ba single data load to page bufer setup ach single data load to page bufer setup ba single data load to page bufer setup 60h * * single data load to page bufer setup 7bh other mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 33 - advance information functional block diagram (8mbit sram) sram part clk gen. row select i/o 1 ~i/o 8 data cont data cont data cont i/o 9 ~i/o 16 vcc vss precharge circuit. memory array 1024 rows 512 16 columns i/o circuit column select we oe ub cs 1 lb control logic cs2 row addresses column addresses functional description 1. x means don t care. (must be low or high state) cs 1 cs2 oe we lb ub i/o1~8 i/o9~16 mode power h x 1) x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 34 - advance information absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions over 1 seconds may affect reliabil ity. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.5 to v cc +0.3v(max. 3.6v) v voltage on vcc supply relative to vss v cc -0.3 to 3.6 v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c recommended dc operating conditions 1) note: 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: v cc +2.0v in case of pulse width 20ns. 3. undershoot: -2.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 2.7 3.0 3.3 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.3 2) v input low voltage v il -0.3 3) - 0.6 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristic 1. typical value are measured at v cc =3.0v, t a =25 c and not 100% tested. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1=v ih or cs2=v il or oe =v ih or we =v il or lb = ub =v ih , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, lb 0.2v or/and ub 0.2v, cs2 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - - 2 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs 1 =v il , cs2=v ih , lb =v il or/and ub =v il , v in =v il or v ih 55ns - - 28 ma output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v standby current(cmos) i sb1 other input =0~vcc 1) cs 1 3 vcc-0.2v, cs2 3 vcc-0.2v( cs 1 controlled) or 2) 0v cs2 0.2v(cs2 controlled) - 0.5 15 m a mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 35 - advance information ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load(see right): c l =100pf+1ttl c l =30pf+1ttl data retention characteristics 1. 1) cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or 2) 0 cs 2 0.2v(cs 2 controlled) 2. typical value are measured at t a =25 c and not 100% tested. item symbol test condition min typ 2) max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 1.5 - 3.3 v data retention current i dr vcc=1.5v, cs 1 3 vcc-0.2v 1) - 0.5 6 m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr trc - - ac characteristics parameter list symbol 55ns units min max read read cycle time t rc 55 - ns address access time t aa - 55 ns chip select to output t co - 55 ns output enable to valid output t oe - 25 ns ub , lb access time t ba - 55 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 20 ns ub , lb disable to high-z output t bhz 0 20 ns output disable to high-z output t ohz 0 20 ns output hold from address change t oh 10 - ns write write cycle time t wc 55 - ns chip select to end of write t cw 45 - ns address set-up time t as 0 - ns address valid to end of write t aw 45 - ns ub , lb valid to end of write t bw 45 - ns write pulse width t wp 40 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 25 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.8v mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 36 - advance information address data out previous data valid data valid timing waveform of read cycle(1) (address controlled , cs 1= oe =v il , cs2= we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs 1 address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs2 sram timing diagrams mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 37 - advance information sram timing diagrams timing waveform of write cycle(2) ( cs 1 controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs 1 cs 2 timing waveform of write cycle(1) ( we controlled) address cs 1 data undefined ub , lb we data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs 2 mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 38 - advance information address data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs 1 or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs 1 controlled v cc 2.7v 2.2v v dr cs 1 vss data retention mode cs 1 3 v cc - 0.2v t sdr t rdr t as(3) cs 1 cs 2 cs 2 controlled v cc 2.7v 0.4v v dr cs 2 vss data retention mode t sdr t rdr cs 2 0.2v mcp memory k5c6481nt(b)m revision 0.0 september 2001 - 39 - advance information package dimension 81-ball tape ball grid array package (measured in millimeters) top view bottom view side view 0.45 0.05 0.08max 0 . 3 2 0 . 0 5 1 . 1 0 0 . 1 0 #a1 1 4 2 7 6 5 3 8 a b c e g d f h 0.80x11=8.80 a 0 . 8 0 x 1 1 = 8 . 8 0 1 0 . 4 0 0 . 1 0 4.40 81- ? 0.45 0.05 9 10 j k 4 . 4 0 0 . 8 0 b 10.8.00 0.10 0.20 m a b ? (datum a) (datum b) l m 1 0 . 4 0 0 . 1 0 10.80 0.10 10.40 0.10 0.80 11 12 |
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